This invention relates to programmable logic devices, and more particularly to circuitry for use in the input and/or output portions of programmable logic devices.
Illustrative programmable logic devices are shown in Cliff et al. U.S. Pat. No. 5,689,195, Huang et al. U.S. Pat. No. 5,764,080, Reddy et al. U.S. Pat. No. 5,977,793, and McClintock et al. U.S. Pat. No. 5,999,016, all of which are hereby incorporated by reference herein in their entireties.
As programmable logic devices become larger and therefore have more input/output ("I/O") pins, the complexity and flexibility with which the user may want to control the various pins tends to increase. The "control" thus referred to includes such functions as output enable, clock, clock enable, clear, etc. because very large programmable logic devices have the capability of performing so many different functions, parallel control of all the I/O pins on the device may not always be compatible with the uses to which the core logic of the device can be put. On the other hand, full individual control of all aspects of the operations of all I/O pins on the device is probably wasteful of device resources, especially since many uses of the device will probably want parallel control of at least some functions of some I/O pins.
In view of the foregoing, it is an object of this invention to provide improved circuitry for controlling I/O pins on programmable logic devices.
It is a more particular object of this invention to provide I/O control circuitry for programmable logic devices which effects a good mix of both parallel and individual control of I/O pin functions and operation.